Semiconductor chips have become progressively more complex, driven in large part by the need for increasing processing power in a smaller chip size. In response, packaging technologies have evolved, for example, to enable an increased lead density, which can reduce the footprint area of a package mounted on a printed circuit board (PCB). Some packaging technologies, such as Quad Flat No Lead (QFN), may enable this increased lead density by providing inner and outer rows of leads connected to a disposable portion of a leadframe. However, manufacturing processes for such leadframes may not be scalable beyond two rows of leads. As lead density requirements further increase, it may be desirable to use packaging technologies that are more scalable in terms of lead density.
Moreover, it may be desirable to further reduce package size in additional ways, such as by reducing package height. At the same time, it may be desirable to maintain sufficient mold locking of leads to a package body. In addition, it may be desirable to facilitate surface mounting of the package to a PCB. For example, it may be difficult to determine how to properly orient the package during surface mounting to the PCB. It may also be desirable to increase the reliability of surface mounting of the package to the PCB. For example, stress due to differential thermal expansion between the leads and the package body may be concentrated at the corners of the package, which can lead to cracking of solder connections to the PCB near the corners of the package, and thus to a decrease in the reliability of surface mounting. It may also be desirable to formulate a packaging process designed to meet these objectives. Current packaging solutions can meet some of these objectives but may not be able to meet most, or all, of these objectives.
It is against this background that a need arose to develop the chip package and associated manufacturing methods described herein.